diff --git a/toplevel.v b/toplevel.v
index f125b65..aaa1d43 100644
--- a/toplevel.v
+++ b/toplevel.v
@@ -37,13 +37,18 @@ DCM #(
    .CLK_FEEDBACK("1X"),   // Specify clock feedback of NONE, 1X or 2X
    .PHASE_SHIFT(0)        // Amount of fixed phase shift, -255 to 255
 ) DCM0 (
-   .CLK0(CLK0),           // CLKOUT w/ 0 degree shift
+   .CLK0(CLK0_DCM),       // CLKOUT w/ 0 degree shift
 //   .CLK2X(CLK_100),       // 2 * CLK0 frequency
 //   .CLKFX(CLKFX),         // DCM CLK synthesis out (M/D)
    .CLKIN(CLKIN),         // Clock input (from IBUFG, BUFG or DCM)
    .CLKFB(CLK0)           // DCM clock feedback
 );
 
+BUFG BUFB0 (
+   .I(CLK0_DCM),
+   .O(CLK0)
+);
+
 wire CLK_O = CLK0;
 reg  RST_O = 1'b1;