module SevenSeg (CLKIN, INPUT, DP, SEG, ANODE);

input         CLKIN;
input  [15:0] INPUT;
input   [3:0] DP;
output  [7:0] SEG;
output  [3:0] ANODE;

reg   [7:0] SEG = 1'b1;
reg   [3:0] ANODE = 4'b1111;

reg  [18:0] CNT;
wire  [1:0] SEG_SEL = CNT[18:17];
reg   [3:0] SEG_BIN;

always @*
begin
   case (SEG_SEL)
      2'b00: SEG_BIN <= INPUT[15:12];
      2'b01: SEG_BIN <= INPUT[11:8];
      2'b10: SEG_BIN <= INPUT[7:4];
      2'b11: SEG_BIN <= INPUT[3:0];
   endcase
end

always @(posedge CLKIN)
begin
   CNT <= CNT + 1;
   
   casex (SEG_SEL)
      2'b00: ANODE <= 4'b0111;
      2'b01: ANODE <= 4'b1011;
      2'b10: ANODE <= 4'b1101;
      2'b11: ANODE <= 4'b1110;
   endcase

   case (SEG_BIN)
      4'h0: SEG[7:1] <= 8'b0000001;
      4'h1: SEG[7:1] <= 8'b1001111;
      4'h2: SEG[7:1] <= 8'b0010010;
      4'h3: SEG[7:1] <= 8'b0000110;
      4'h4: SEG[7:1] <= 8'b1001100;
      4'h5: SEG[7:1] <= 8'b0100100;
      4'h6: SEG[7:1] <= 8'b0100000;
      4'h7: SEG[7:1] <= 8'b0001111;
      4'h8: SEG[7:1] <= 8'b0000000;
      4'h9: SEG[7:1] <= 8'b0000100;
      4'hA: SEG[7:1] <= 8'b0001000;
      4'hB: SEG[7:1] <= 8'b1100000;
      4'hC: SEG[7:1] <= 8'b0110001;
      4'hD: SEG[7:1] <= 8'b1000010;
      4'hE: SEG[7:1] <= 8'b0110000;
      4'hF: SEG[7:1] <= 8'b0111000;
   endcase

   case (SEG_SEL)
      2'b00: SEG[0] <= ~DP[3];
      2'b01: SEG[0] <= ~DP[2];
      2'b10: SEG[0] <= ~DP[1];
      2'b11: SEG[0] <= ~DP[0];
   endcase
end

endmodule