module StackRAM (CLKIN, ADDR_A, WE_A, IN_A, OUT_A, ADDR_B, OUT_B);

parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 32;

input CLKIN;
input [ADDR_WIDTH-1:0] ADDR_A;
input WE_A;
input [DATA_WIDTH-1:0] IN_A;
output [DATA_WIDTH-1:0] OUT_A;
input [ADDR_WIDTH-1:0] ADDR_B;
output [DATA_WIDTH-1:0] OUT_B;

reg [DATA_WIDTH-1:0] RAM[0:(1<<ADDR_WIDTH)-1];
reg [ADDR_WIDTH-1:0] READ_A;
reg [ADDR_WIDTH-1:0] READ_B;

assign OUT_A = RAM[READ_A];
assign OUT_B = RAM[READ_B];

always @(posedge CLKIN)
begin
   if (WE_A)
      RAM[ADDR_A] <= IN_A;

   READ_A <= ADDR_A;
end

always @(negedge CLKIN)
begin
   READ_B <= ADDR_B;
end

endmodule