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#                                                                     #
# Pin Description for the Spartan-3 Starter Kit Board                 #
#                                                                     #
#######################################################################

#
# 50 MHz on-board clock source
#
NET "CLKIN" LOC = T9;
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 20 ns HIGH 50%;

OFFSET = OUT 20 ns AFTER "CLKIN";

#
# On-board Static RAM
#
TIMEGRP "SRAM_ADR" = PADS("SRAM_ADR<*>");
TIMEGRP "SRAM_IO"  = PADS("SRAM_IO?<*>");
TIMEGRP "SRAM_CE"  = PADS("SRAM_CE?");
TIMEGRP "SRAM_BE"  = PADS("SRAM_UB?") PADS("SRAM_LB?");
TIMEGRP "SRAM_WE"  = PADS("SRAM_WE");
TIMEGRP "SRAM_OE"  = PADS("SRAM_OE");

TIMEGRP "SRAM_ADR" OFFSET = OUT  6.0 ns AFTER "CLKIN";
TIMEGRP "SRAM_IO"  OFFSET = IN  15.0 ns VALID 20 ns AFTER "CLKIN";
#TIMEGRP "SRAM_CE"  OFFSET = OUT  2.0 ns AFTER "CLKIN";
TIMEGRP "SRAM_BE"  OFFSET = OUT  8.0 ns AFTER "CLKIN";
TIMEGRP "SRAM_OE"  OFFSET = OUT  8.0 ns AFTER "CLKIN";

TIMEGRP "SRAM_IO"  OFFSET = OUT 14.0 ns AFTER "CLKIN";
TIMEGRP "SRAM_WE"  OFFSET = OUT 18.0 ns AFTER "CLKIN";

NET "SRAM_ADR<*>"  DRIVE = 4;
NET "SRAM_IO1<*>"  DRIVE = 4;
NET "SRAM_IO2<*>"  DRIVE = 4;
NET "SRAM_CE?"     DRIVE = 4;
NET "SRAM_UB?"     DRIVE = 4;
NET "SRAM_LB?"     DRIVE = 4;
NET "SRAM_WE"      DRIVE = 4;
NET "SRAM_OE"      DRIVE = 4;

NET "SRAM_ADR<*>"  FAST;
NET "SRAM_IO1<*>"  FAST;
NET "SRAM_IO2<*>"  FAST;
NET "SRAM_CE?"     FAST;
NET "SRAM_UB?"     FAST;
NET "SRAM_LB?"     FAST;
NET "SRAM_WE"      FAST;
NET "SRAM_OE"      FAST;

NET "SRAM_ADR<17>" LOC = L3;   # Address to SRAM bus
NET "SRAM_ADR<16>" LOC = K5;
NET "SRAM_ADR<15>" LOC = K3;
NET "SRAM_ADR<14>" LOC = J3;
NET "SRAM_ADR<13>" LOC = J4;
NET "SRAM_ADR<12>" LOC = H4;
NET "SRAM_ADR<11>" LOC = H3;
NET "SRAM_ADR<10>" LOC = G5;
NET "SRAM_ADR<9>"  LOC = E4;
NET "SRAM_ADR<8>"  LOC = E3;
NET "SRAM_ADR<7>"  LOC = F4;
NET "SRAM_ADR<6>"  LOC = F3;
NET "SRAM_ADR<5>"  LOC = G4;
NET "SRAM_ADR<4>"  LOC = L4;
NET "SRAM_ADR<3>"  LOC = M3;
NET "SRAM_ADR<2>"  LOC = M4;
NET "SRAM_ADR<1>"  LOC = N3;
NET "SRAM_ADR<0>"  LOC = L5;

NET "SRAM_IO1<15>" LOC = R1;   # Data to and/or from SRAM #1
NET "SRAM_IO1<14>" LOC = P1;
NET "SRAM_IO1<13>" LOC = L2;
NET "SRAM_IO1<12>" LOC = J2;
NET "SRAM_IO1<11>" LOC = H1;
NET "SRAM_IO1<10>" LOC = F2;
NET "SRAM_IO1<9>"  LOC = P8;
NET "SRAM_IO1<8>"  LOC = D3;
NET "SRAM_IO1<7>"  LOC = B1;
NET "SRAM_IO1<6>"  LOC = C1;
NET "SRAM_IO1<5>"  LOC = C2;
NET "SRAM_IO1<4>"  LOC = R5;
NET "SRAM_IO1<3>"  LOC = T5;
NET "SRAM_IO1<2>"  LOC = R6;
NET "SRAM_IO1<1>"  LOC = T8;
NET "SRAM_IO1<0>"  LOC = N7;

NET "SRAM_CE1"     LOC = P7;   # Control signals to SRAM #1
NET "SRAM_UB1"     LOC = T4;
NET "SRAM_LB1"     LOC = P6;

NET "SRAM_IO2<15>" LOC = N1;   # Data to/from SRAM #2
NET "SRAM_IO2<14>" LOC = M1;
NET "SRAM_IO2<13>" LOC = K2;
NET "SRAM_IO2<12>" LOC = C3;
NET "SRAM_IO2<11>" LOC = F5;
NET "SRAM_IO2<10>" LOC = G1;
NET "SRAM_IO2<9>"  LOC = E2;
NET "SRAM_IO2<8>"  LOC = D2;
NET "SRAM_IO2<7>"  LOC = D1;
NET "SRAM_IO2<6>"  LOC = E1;
NET "SRAM_IO2<5>"  LOC = G2;
NET "SRAM_IO2<4>"  LOC = J1;
NET "SRAM_IO2<3>"  LOC = K1;
NET "SRAM_IO2<2>"  LOC = M2;
NET "SRAM_IO2<1>"  LOC = N2;
NET "SRAM_IO2<0>"  LOC = P2;

NET "SRAM_CE2"     LOC = N5;   # Control signals to SRAM #2
NET "SRAM_UB2"     LOC = R4;
NET "SRAM_LB2"     LOC = P5;

NET "SRAM_WE"      LOC = G3;   # Control signals to SRAMs #1 and #2
NET "SRAM_OE"      LOC = K4;

#
# RS-232 Serial Port (w/ DB-9)
#
TIMEGRP "RS232" = PADS("RX_A") PADS("TX_A");
NET "TX_A"         DRIVE = 4;

NET "RX_A"         LOC = T13;  # serial input from V.24 driver
NET "TX_A"         LOC = R13;  # serial output to V.24 driver

#
# On-board LEDs
#
TIMEGRP "LEDS" = PADS("LED<*>");
NET "LED<*>"       DRIVE = 4;

NET "LED<7>"       LOC = P11;  # signal to 8 LEDs (7 is leftmost)
NET "LED<6>"       LOC = P12;
NET "LED<5>"       LOC = N12;
NET "LED<4>"       LOC = P13;
NET "LED<3>"       LOC = N14;
NET "LED<2>"       LOC = L12;
NET "LED<1>"       LOC = P14;
NET "LED<0>"       LOC = K12;

#
# On-board 7-segment LED displays
#
TIMEGRP "DISPLAY" = PADS("SEG<*>") PADS("ANODE<*>");
NET "SEG<*>"       DRIVE = 4;
NET "ANODE<*>"     DRIVE = 4;

NET "SEG<7>"       LOC = E14;  # (a) signal to 7-segment displays
NET "SEG<6>"       LOC = G13;  # (b)
NET "SEG<5>"       LOC = N15;  # (c) Note: active-low outputs
NET "SEG<4>"       LOC = P15;  # (d)
NET "SEG<3>"       LOC = R16;  # (e)
NET "SEG<2>"       LOC = F13;  # (f)
NET "SEG<1>"       LOC = N16;  # (g)
NET "SEG<0>"       LOC = P16;  # (dp)

NET "ANODE<3>"     LOC = E13;  # selector for SEG<> (3 is leftmost)
NET "ANODE<2>"     LOC = F14;
NET "ANODE<1>"     LOC = G14;  # Note: active-low outputs
NET "ANODE<0>"     LOC = D14;

#
# On-board slide switches
#
TIMEGRP "SWITCHES" = PADS("SWITCH<*>");

NET "SWITCH<7>"    LOC = K13;  # signal from slide switches (7 is leftmost)
NET "SWITCH<6>"    LOC = K14;
NET "SWITCH<5>"    LOC = J13;
NET "SWITCH<4>"    LOC = J14;
NET "SWITCH<3>"    LOC = H13;
NET "SWITCH<2>"    LOC = H14;
NET "SWITCH<1>"    LOC = G12;
NET "SWITCH<0>"    LOC = F12;

#
#  On-board pushbuttons
#
TIMEGRP "BUTTONS" = PADS("BTN<*>");

NET "BTN<3>"       LOC = L14;  # signal from push-buttons (3 is leftmost)
NET "BTN<2>"       LOC = L13;
NET "BTN<1>"       LOC = M14;
NET "BTN<0>"       LOC = M13;

#
# On-board 3-bit VGA port
#

#TIMEGRP "VGA" = PADS("VGA_*");

#NET "VGA_*"        DRIVE = 4;

#NET "VGA_RED"      LOC = R12;  # Output to 3-bit VGA display interface
#NET "VGA_GREEN"    LOC = T12;
#NET "VGA_BLUE"     LOC = R11;
#NET "VGA_H_SYNC"   LOC = R9;
#NET "VGA_V_SYNC"   LOC = T10;

#
# On-board PS/2 keyboard/mouse port
#

#TIMEGRP "PS2" = PADS("PS2_*");

#NET "PS2_CLK"      DRIVE = 4;

#NET "PS2_DATA"     LOC = M15;  # Input from PS/2 keyboard/mouse port
#NET "PS2_CLK"      LOC = M16;