51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
// Computes the number of leading zeros in the input. Result is 0...32.
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module NLZ (IN, OUT);
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input [31:0] IN;
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output [5:0] OUT;
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wire [7:0] PARTS = {
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|IN[31:28], |IN[27:24], |IN[23:20], |IN[19:16],
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|IN[15:12], |IN[11: 8], |IN[ 7: 4], |IN[ 3: 0]
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};
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// synthesis attribute priority_extract of LEADING_PARTS is force;
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reg [2:0] LEADING_PARTS;
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reg [1:0] LEADING_BITS;
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reg [3:0] PART;
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always @*
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begin
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if (PARTS[7]) LEADING_PARTS <= 3'b000;
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else if (PARTS[6]) LEADING_PARTS <= 3'b001;
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else if (PARTS[5]) LEADING_PARTS <= 3'b010;
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else if (PARTS[4]) LEADING_PARTS <= 3'b011;
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else if (PARTS[3]) LEADING_PARTS <= 3'b100;
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else if (PARTS[2]) LEADING_PARTS <= 3'b101;
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else if (PARTS[1]) LEADING_PARTS <= 3'b110;
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else if (PARTS[0]) LEADING_PARTS <= 3'b111;
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else LEADING_PARTS <= 3'bXXX;
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case (LEADING_PARTS)
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3'b000: PART <= IN[31:28];
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3'b001: PART <= IN[27:24];
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3'b010: PART <= IN[23:20];
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3'b011: PART <= IN[19:16];
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3'b100: PART <= IN[15:12];
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3'b101: PART <= IN[11: 8];
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3'b110: PART <= IN[ 7: 4];
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3'b111: PART <= IN[ 3: 0];
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endcase
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casex (PART)
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4'b1XXX: LEADING_BITS <= 2'b00;
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4'b01XX: LEADING_BITS <= 2'b01;
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4'b001X: LEADING_BITS <= 2'b10;
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4'b000X: LEADING_BITS <= 2'b11;
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endcase
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end
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assign OUT = (~|PARTS) ? 6'd32 : { LEADING_PARTS, LEADING_BITS };
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endmodule
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