65 lines
1.4 KiB
Verilog
65 lines
1.4 KiB
Verilog
module SevenSeg (CLKIN, INPUT, DP, SEG, ANODE);
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input CLKIN;
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input [15:0] INPUT;
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input [3:0] DP;
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output [7:0] SEG;
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output [3:0] ANODE;
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reg [7:0] SEG = 1'b1;
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reg [3:0] ANODE = 4'b1111;
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reg [18:0] CNT;
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wire [1:0] SEG_SEL = CNT[18:17];
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reg [3:0] SEG_BIN;
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always @*
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begin
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case (SEG_SEL)
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2'b00: SEG_BIN <= INPUT[15:12];
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2'b01: SEG_BIN <= INPUT[11:8];
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2'b10: SEG_BIN <= INPUT[7:4];
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2'b11: SEG_BIN <= INPUT[3:0];
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endcase
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end
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always @(posedge CLKIN)
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begin
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CNT <= CNT + 1;
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casex (SEG_SEL)
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2'b00: ANODE <= 4'b0111;
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2'b01: ANODE <= 4'b1011;
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2'b10: ANODE <= 4'b1101;
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2'b11: ANODE <= 4'b1110;
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endcase
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case (SEG_BIN)
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4'h0: SEG[7:1] <= 8'b0000001;
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4'h1: SEG[7:1] <= 8'b1001111;
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4'h2: SEG[7:1] <= 8'b0010010;
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4'h3: SEG[7:1] <= 8'b0000110;
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4'h4: SEG[7:1] <= 8'b1001100;
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4'h5: SEG[7:1] <= 8'b0100100;
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4'h6: SEG[7:1] <= 8'b0100000;
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4'h7: SEG[7:1] <= 8'b0001111;
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4'h8: SEG[7:1] <= 8'b0000000;
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4'h9: SEG[7:1] <= 8'b0000100;
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4'hA: SEG[7:1] <= 8'b0001000;
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4'hB: SEG[7:1] <= 8'b1100000;
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4'hC: SEG[7:1] <= 8'b0110001;
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4'hD: SEG[7:1] <= 8'b1000010;
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4'hE: SEG[7:1] <= 8'b0110000;
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4'hF: SEG[7:1] <= 8'b0111000;
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endcase
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case (SEG_SEL)
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2'b00: SEG[0] <= ~DP[3];
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2'b01: SEG[0] <= ~DP[2];
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2'b10: SEG[0] <= ~DP[1];
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2'b11: SEG[0] <= ~DP[0];
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endcase
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end
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endmodule
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