35 lines
627 B
Verilog
35 lines
627 B
Verilog
module StackRAM (CLKIN, ADDR_A, WE_A, IN_A, OUT_A, ADDR_B, OUT_B);
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parameter ADDR_WIDTH = 9;
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parameter DATA_WIDTH = 32;
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input CLKIN;
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input [ADDR_WIDTH-1:0] ADDR_A;
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input WE_A;
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input [DATA_WIDTH-1:0] IN_A;
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output [DATA_WIDTH-1:0] OUT_A;
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input [ADDR_WIDTH-1:0] ADDR_B;
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output [DATA_WIDTH-1:0] OUT_B;
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reg [DATA_WIDTH-1:0] RAM[0:(1<<ADDR_WIDTH)-1];
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reg [ADDR_WIDTH-1:0] READ_A;
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reg [ADDR_WIDTH-1:0] READ_B;
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assign OUT_A = RAM[READ_A];
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assign OUT_B = RAM[READ_B];
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always @(posedge CLKIN)
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begin
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if (WE_A)
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RAM[ADDR_A] <= IN_A;
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READ_A <= ADDR_A;
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end
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always @(negedge CLKIN)
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begin
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READ_B <= ADDR_B;
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end
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endmodule
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