80 lines
2.4 KiB
Verilog
80 lines
2.4 KiB
Verilog
// Simple 2:1 alternating (round-robin) arbiter.
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// Switches master on ACK from slave unless selected master asserts LOCK.
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// Data from slave is sent to both masters. Address and data bus widths
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// are configurable, as is granularity. Default is 32-bit addresses and
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// data with byte granularity.
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module WB_ARB_2M (CLK_I, RST_I, SELECT_O,
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M0_ADR_I, M0_DAT_I, M0_DAT_O, M0_LOCK_I, M0_CYC_I, M0_STB_I,
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M0_WE_I, M0_SEL_I, M0_ACK_O, M0_ERR_O, M0_RTY_O,
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M1_ADR_I, M1_DAT_I, M1_DAT_O, M1_LOCK_I, M1_CYC_I, M1_STB_I,
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M1_WE_I, M1_SEL_I, M1_ACK_O, M1_ERR_O, M1_RTY_O,
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S_ADR_O, S_DAT_O, S_DAT_I, S_LOCK_O, S_CYC_O, S_STB_O,
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S_WE_O, S_SEL_O, S_ACK_I, S_ERR_I, S_RTY_I);
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parameter ADDR_WIDTH = 30;
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parameter DATA_WIDTH = 32;
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parameter SEL_WIDTH = 4;
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input CLK_I, RST_I;
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output SELECT_O;
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input [ADDR_WIDTH-1:0] M0_ADR_I, M1_ADR_I;
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input [DATA_WIDTH-1:0] M0_DAT_I, M1_DAT_I;
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output [DATA_WIDTH-1:0] M0_DAT_O, M1_DAT_O;
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input M0_LOCK_I, M1_LOCK_I;
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input M0_CYC_I, M1_CYC_I;
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input M0_STB_I, M1_STB_I;
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input M0_WE_I, M1_WE_I;
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input [SEL_WIDTH-1:0] M0_SEL_I, M1_SEL_I;
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output M0_ACK_O, M1_ACK_O;
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output M0_ERR_O, M1_ERR_O;
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output M0_RTY_O, M1_RTY_O;
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output [ADDR_WIDTH-1:0] S_ADR_O;
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output [DATA_WIDTH-1:0] S_DAT_O;
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input [DATA_WIDTH-1:0] S_DAT_I;
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output S_LOCK_O, S_CYC_O;
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output S_STB_O, S_WE_O;
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output [SEL_WIDTH-1:0] S_SEL_O;
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input S_ACK_I, S_ERR_I, S_RTY_I;
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reg SELECT_O = 1'bX;
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assign M0_DAT_O = ~SELECT_O ? S_DAT_I : 256'dX;
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assign M1_DAT_O = SELECT_O ? S_DAT_I : 256'dX;
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assign M0_ACK_O = S_ACK_I & ~SELECT_O;
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assign M1_ACK_O = S_ACK_I & SELECT_O;
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assign M0_ERR_O = S_ERR_I & ~SELECT_O;
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assign M1_ERR_O = S_ERR_I & SELECT_O;
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assign M0_RTY_O = S_RTY_I & ~SELECT_O;
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assign M1_RTY_O = S_RTY_I & SELECT_O;
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assign S_ADR_O = SELECT_O ? M1_ADR_I : M0_ADR_I;
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assign S_DAT_O = SELECT_O ? M1_DAT_I : M0_DAT_I;
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assign S_LOCK_O = SELECT_O ? M1_LOCK_I : M0_LOCK_I;
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assign S_CYC_O = SELECT_O ? M1_CYC_I : M0_CYC_I;
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assign S_STB_O = SELECT_O ? M1_STB_I : M0_STB_I;
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assign S_WE_O = SELECT_O ? M1_WE_I : M0_WE_I;
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assign S_SEL_O = SELECT_O ? M1_SEL_I : M0_SEL_I;
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wire CYC_END = (S_ACK_I | S_ERR_I | S_RTY_I);
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always @(posedge CLK_I)
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begin
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casex ({S_LOCK_O, CYC_END, M1_CYC_I, M0_CYC_I})
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4'b1XXX: SELECT_O <= SELECT_O;
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4'b0111: SELECT_O <= ~SELECT_O;
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4'b0X10: SELECT_O <= 1'b1;
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4'b0X01: SELECT_O <= 1'b0;
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4'b0XXX: SELECT_O <= SELECT_O;
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endcase
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end
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endmodule
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