210 lines
5.8 KiB
Plaintext
210 lines
5.8 KiB
Plaintext
#######################################################################
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# #
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# Pin Description for the Spartan-3 Starter Kit Board #
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# #
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#######################################################################
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#
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# 50 MHz on-board clock source
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#
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NET "CLKIN" LOC = T9;
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NET "CLKIN" TNM_NET = "CLKIN";
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TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 20 ns HIGH 50%;
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OFFSET = OUT 20 ns AFTER "CLKIN";
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#
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# On-board Static RAM
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#
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TIMEGRP "SRAM_ADR" = PADS("SRAM_ADR<*>");
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TIMEGRP "SRAM_IO" = PADS("SRAM_IO?<*>");
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TIMEGRP "SRAM_CE" = PADS("SRAM_CE?");
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TIMEGRP "SRAM_BE" = PADS("SRAM_UB?") PADS("SRAM_LB?");
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TIMEGRP "SRAM_WE" = PADS("SRAM_WE");
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TIMEGRP "SRAM_OE" = PADS("SRAM_OE");
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TIMEGRP "SRAM_ADR" OFFSET = OUT 6.0 ns AFTER "CLKIN";
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TIMEGRP "SRAM_IO" OFFSET = IN 15.0 ns VALID 20 ns AFTER "CLKIN";
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#TIMEGRP "SRAM_CE" OFFSET = OUT 2.0 ns AFTER "CLKIN";
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TIMEGRP "SRAM_BE" OFFSET = OUT 8.0 ns AFTER "CLKIN";
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TIMEGRP "SRAM_OE" OFFSET = OUT 8.0 ns AFTER "CLKIN";
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TIMEGRP "SRAM_IO" OFFSET = OUT 14.0 ns AFTER "CLKIN";
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TIMEGRP "SRAM_WE" OFFSET = OUT 18.0 ns AFTER "CLKIN";
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NET "SRAM_ADR<*>" DRIVE = 4;
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NET "SRAM_IO1<*>" DRIVE = 4;
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NET "SRAM_IO2<*>" DRIVE = 4;
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NET "SRAM_CE?" DRIVE = 4;
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NET "SRAM_UB?" DRIVE = 4;
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NET "SRAM_LB?" DRIVE = 4;
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NET "SRAM_WE" DRIVE = 4;
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NET "SRAM_OE" DRIVE = 4;
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NET "SRAM_ADR<*>" FAST;
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NET "SRAM_IO1<*>" FAST;
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NET "SRAM_IO2<*>" FAST;
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NET "SRAM_CE?" FAST;
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NET "SRAM_UB?" FAST;
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NET "SRAM_LB?" FAST;
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NET "SRAM_WE" FAST;
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NET "SRAM_OE" FAST;
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NET "SRAM_ADR<17>" LOC = L3; # Address to SRAM bus
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NET "SRAM_ADR<16>" LOC = K5;
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NET "SRAM_ADR<15>" LOC = K3;
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NET "SRAM_ADR<14>" LOC = J3;
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NET "SRAM_ADR<13>" LOC = J4;
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NET "SRAM_ADR<12>" LOC = H4;
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NET "SRAM_ADR<11>" LOC = H3;
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NET "SRAM_ADR<10>" LOC = G5;
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NET "SRAM_ADR<9>" LOC = E4;
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NET "SRAM_ADR<8>" LOC = E3;
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NET "SRAM_ADR<7>" LOC = F4;
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NET "SRAM_ADR<6>" LOC = F3;
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NET "SRAM_ADR<5>" LOC = G4;
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NET "SRAM_ADR<4>" LOC = L4;
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NET "SRAM_ADR<3>" LOC = M3;
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NET "SRAM_ADR<2>" LOC = M4;
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NET "SRAM_ADR<1>" LOC = N3;
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NET "SRAM_ADR<0>" LOC = L5;
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NET "SRAM_IO1<15>" LOC = R1; # Data to and/or from SRAM #1
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NET "SRAM_IO1<14>" LOC = P1;
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NET "SRAM_IO1<13>" LOC = L2;
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NET "SRAM_IO1<12>" LOC = J2;
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NET "SRAM_IO1<11>" LOC = H1;
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NET "SRAM_IO1<10>" LOC = F2;
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NET "SRAM_IO1<9>" LOC = P8;
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NET "SRAM_IO1<8>" LOC = D3;
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NET "SRAM_IO1<7>" LOC = B1;
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NET "SRAM_IO1<6>" LOC = C1;
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NET "SRAM_IO1<5>" LOC = C2;
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NET "SRAM_IO1<4>" LOC = R5;
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NET "SRAM_IO1<3>" LOC = T5;
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NET "SRAM_IO1<2>" LOC = R6;
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NET "SRAM_IO1<1>" LOC = T8;
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NET "SRAM_IO1<0>" LOC = N7;
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NET "SRAM_CE1" LOC = P7; # Control signals to SRAM #1
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NET "SRAM_UB1" LOC = T4;
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NET "SRAM_LB1" LOC = P6;
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NET "SRAM_IO2<15>" LOC = N1; # Data to/from SRAM #2
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NET "SRAM_IO2<14>" LOC = M1;
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NET "SRAM_IO2<13>" LOC = K2;
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NET "SRAM_IO2<12>" LOC = C3;
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NET "SRAM_IO2<11>" LOC = F5;
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NET "SRAM_IO2<10>" LOC = G1;
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NET "SRAM_IO2<9>" LOC = E2;
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NET "SRAM_IO2<8>" LOC = D2;
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NET "SRAM_IO2<7>" LOC = D1;
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NET "SRAM_IO2<6>" LOC = E1;
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NET "SRAM_IO2<5>" LOC = G2;
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NET "SRAM_IO2<4>" LOC = J1;
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NET "SRAM_IO2<3>" LOC = K1;
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NET "SRAM_IO2<2>" LOC = M2;
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NET "SRAM_IO2<1>" LOC = N2;
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NET "SRAM_IO2<0>" LOC = P2;
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NET "SRAM_CE2" LOC = N5; # Control signals to SRAM #2
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NET "SRAM_UB2" LOC = R4;
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NET "SRAM_LB2" LOC = P5;
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NET "SRAM_WE" LOC = G3; # Control signals to SRAMs #1 and #2
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NET "SRAM_OE" LOC = K4;
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#
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# RS-232 Serial Port (w/ DB-9)
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#
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TIMEGRP "RS232" = PADS("RX_A") PADS("TX_A");
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NET "TX_A" DRIVE = 4;
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NET "RX_A" LOC = T13; # serial input from V.24 driver
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NET "TX_A" LOC = R13; # serial output to V.24 driver
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#
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# On-board LEDs
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#
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TIMEGRP "LEDS" = PADS("LED<*>");
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NET "LED<*>" DRIVE = 4;
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NET "LED<7>" LOC = P11; # signal to 8 LEDs (7 is leftmost)
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NET "LED<6>" LOC = P12;
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NET "LED<5>" LOC = N12;
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NET "LED<4>" LOC = P13;
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NET "LED<3>" LOC = N14;
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NET "LED<2>" LOC = L12;
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NET "LED<1>" LOC = P14;
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NET "LED<0>" LOC = K12;
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#
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# On-board 7-segment LED displays
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#
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TIMEGRP "DISPLAY" = PADS("SEG<*>") PADS("ANODE<*>");
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NET "SEG<*>" DRIVE = 4;
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NET "ANODE<*>" DRIVE = 4;
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NET "SEG<7>" LOC = E14; # (a) signal to 7-segment displays
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NET "SEG<6>" LOC = G13; # (b)
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NET "SEG<5>" LOC = N15; # (c) Note: active-low outputs
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NET "SEG<4>" LOC = P15; # (d)
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NET "SEG<3>" LOC = R16; # (e)
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NET "SEG<2>" LOC = F13; # (f)
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NET "SEG<1>" LOC = N16; # (g)
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NET "SEG<0>" LOC = P16; # (dp)
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NET "ANODE<3>" LOC = E13; # selector for SEG<> (3 is leftmost)
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NET "ANODE<2>" LOC = F14;
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NET "ANODE<1>" LOC = G14; # Note: active-low outputs
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NET "ANODE<0>" LOC = D14;
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#
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# On-board slide switches
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#
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TIMEGRP "SWITCHES" = PADS("SWITCH<*>");
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NET "SWITCH<7>" LOC = K13; # signal from slide switches (7 is leftmost)
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NET "SWITCH<6>" LOC = K14;
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NET "SWITCH<5>" LOC = J13;
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NET "SWITCH<4>" LOC = J14;
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NET "SWITCH<3>" LOC = H13;
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NET "SWITCH<2>" LOC = H14;
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NET "SWITCH<1>" LOC = G12;
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NET "SWITCH<0>" LOC = F12;
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#
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# On-board pushbuttons
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#
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TIMEGRP "BUTTONS" = PADS("BTN<*>");
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NET "BTN<3>" LOC = L14; # signal from push-buttons (3 is leftmost)
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NET "BTN<2>" LOC = L13;
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NET "BTN<1>" LOC = M14;
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NET "BTN<0>" LOC = M13;
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#
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# On-board 3-bit VGA port
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#
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#TIMEGRP "VGA" = PADS("VGA_*");
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#NET "VGA_*" DRIVE = 4;
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#NET "VGA_RED" LOC = R12; # Output to 3-bit VGA display interface
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#NET "VGA_GREEN" LOC = T12;
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#NET "VGA_BLUE" LOC = R11;
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#NET "VGA_H_SYNC" LOC = R9;
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#NET "VGA_V_SYNC" LOC = T10;
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#
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# On-board PS/2 keyboard/mouse port
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#
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#TIMEGRP "PS2" = PADS("PS2_*");
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#NET "PS2_CLK" DRIVE = 4;
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#NET "PS2_DATA" LOC = M15; # Input from PS/2 keyboard/mouse port
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#NET "PS2_CLK" LOC = M16;
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